Kenichi Kuroda

According to our database1, Kenichi Kuroda authored at least 21 papers between 2001 and 2017.

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Bibliography

2017
Studies on stabilizing a massive PV penetrated power system using VSG.
Proceedings of the 2017 IEEE PES Innovative Smart Grid Technologies Conference Europe, 2017

2014
Real-time grid simulation platform for system analysis using virtual power source.
Proceedings of the 2014 Power Systems Computation Conference, 2014

2012
Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

2011
Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
J. Supercomput., 2011

2010
Orbital Systolic Algorithms and Array Processors for Solution of the Algebraic Path Problem.
IEICE Trans. Inf. Syst., 2010

An Efficient Algorithm and Embedded Multicore Implementation of ECG Analysis in Multi-lead Electrocardiogram Records.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Advanced Design Issues for OASIS Network-on-Chip Architecture.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010

2008
Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems.
J. Comput., 2008

A Modeling of a Dynamically Reconfigurable Processor Using SystemC.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Optimizing Two-Dimensional Continuous Dynamic Programming for Cell Broadband Engine Processors.
Proceedings of the Japan-China Joint Workshop on Frontier of Computer Science and Technology, 2008

Single Instruction Dual-Execution Model Processor Architecture.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

Implementation of a combined autocorrelation method for real-time tissue elasticity imaging on FPGA.
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

Arithmetic precision of the Generalized Hebbian Algorithm for hardware implementation.
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2007
Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem.
Proceedings of the FPL 2007, 2007

2006
A Hardware Resource Management System for Adaptive Computing on Dynamically Reconfigurable Devices.
Proceedings of the Japan-China Joint Workshop on Frontier of Computer Science and Technology, 2006

2005
A Master-Slave Adaptive Load-Distribution Processor Model on PCA.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2003
Reconfigurable Instruction-Level Parallel Processor Architecture.
Proceedings of the Advances in Computer Systems Architecture, 2003

2001
Universal-V<sub>dd</sub> 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell.
IEEE J. Solid State Circuits, 2001


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