Kenichi Kawasaki

According to our database1, Kenichi Kawasaki authored at least 7 papers between 2006 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
A versatile multi-modality serial link.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect.
IEEE J. Solid State Circuits, 2011

A 12.5+12.5Gb/s full-duplex plastic waveguide interconnect.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A Millimeter-Wave Intra-Connect Solution.
IEEE J. Solid State Circuits, 2010

2009
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support.
IEEE J. Solid State Circuits, 2009

2006
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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