Kenichi Imamiya

According to our database, Kenichi Imamiya authored at least 12 papers between 1990 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory.

Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue, Toshiyuki Takahashi, Toshifumi Shano, Yukio Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Noriaki Motohashi, Kazuhisa Kanazawa, Kenichi Imamiya, Hiroto Nakai, Menahem Lasser, Mark Murin, Avraham Meir, Arik Eyal, Mark Shlick

IEEE J. Solid State Circuits, 2008

2002

A 125-mm² 1-Gb NAND flash memory with 10-MByte/s program speed.

Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che

IEEE J. Solid State Circuits, 2002

2000

A source-line programming scheme for low-voltage operation NAND flash memories.

Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui

IEEE J. Solid State Circuits, 2000

1999

A negative V_th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.

Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui

IEEE J. Solid State Circuits, 1999

A 130-mm/², 256-Mbit NAND flash with shallow trench isolation technology.

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

IEEE J. Solid State Circuits, 1999

1995

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM.

Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto

IEEE J. Solid State Circuits, November, 1995

1992

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure.

Akira Umezawa, Shigeru Atsumi, Masao Kuriyama, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsushi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka

IEEE J. Solid State Circuits, November, 1992

Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation.

Ken-ichi Imamiya, Jun-ichi Miyamoto, Nobuaki Ohtuska, Naoto Tomita, Yumiko Iyama

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique.

Naoto Tomita, Nobuaki Ohtsuka, Jun-ichi Miyamoto, Ken-ichi Imamiya, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Norihisa Arai, Yukio Kaneko, Eiji Sakagami, Kuniyoshi Yoshikawa, Sumio Tanaka

IEEE J. Solid State Circuits, November, 1991

Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme.

Jun-ichi Miyamoto, Nobuaki Ohtsuka, Ken-ichi Imamiya, Naoto Tomita, Yumiko Iyama

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

A 16-ns 1-Mb CMOS EPROM.

Masao Kuriyama, Shigeru Atsumi, Ken-ichi Imamiya, Yumiko Iyama, Naohiro Matsukawa, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Sumio Tanaka

IEEE J. Solid State Circuits, October, 1990

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design.

Kenichi Imamiya, Jun-ichi Miyamoto, Shigeru Atsumi, Nobuaki Ohtsuka, Yukinori Muroya, Toshiyuki Sako, Masao Higashino, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Hitoshi Araki, Yukio Kaneko, Kazuhito Narita, Norihisa Arai, Kuniyoshi Yoshikawa, Shinichi Tanaka

IEEE J. Solid State Circuits, February, 1990