Kenichi Imamiya

According to our database1, Kenichi Imamiya authored at least 12 papers between 1990 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory.
IEEE J. Solid State Circuits, 2008

2002
A 125-mm<sup>2</sup> 1-Gb NAND flash memory with 10-MByte/s program speed.
IEEE J. Solid State Circuits, 2002

2000
A source-line programming scheme for low-voltage operation NAND flash memories.
IEEE J. Solid State Circuits, 2000

1999
A negative V<sub>th</sub> cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.
IEEE J. Solid State Circuits, 1999

A 130-mm/<sup>2</sup>, 256-Mbit NAND flash with shallow trench isolation technology.
IEEE J. Solid State Circuits, 1999

1995
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM.
IEEE J. Solid State Circuits, November, 1995

1992
A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure.
IEEE J. Solid State Circuits, November, 1992

Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991
A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique.
IEEE J. Solid State Circuits, November, 1991

Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
A 16-ns 1-Mb CMOS EPROM.
IEEE J. Solid State Circuits, October, 1990

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design.
IEEE J. Solid State Circuits, February, 1990


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