Kenichi Imamiya
According to our database1,
Kenichi Imamiya
authored at least 12 papers
between 1990 and 2008.
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Bibliography
2008
2002
IEEE J. Solid State Circuits, 2002
2000
IEEE J. Solid State Circuits, 2000
1999
A negative V<sub>th</sub> cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
1995
IEEE J. Solid State Circuits, November, 1995
1992
A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure.
IEEE J. Solid State Circuits, November, 1992
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
1991
IEEE J. Solid State Circuits, November, 1991
Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
1990
IEEE J. Solid State Circuits, February, 1990