Kenichi Ichino

According to our database, Kenichi Ichino authored at least 6 papers between 2001 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development.

Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa

J. Inf. Process. Syst., 2008

2004

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits.

Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2004

Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters.

Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Seed Selection Procedure for LFSR-Based Random Pattern Generators.

Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.

Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2001

Hybrid BIST Using Partially Rotational Scan.

Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001