Ken Takeuchi
Orcid: 0000-0002-9345-6503
According to our database1,
Ken Takeuchi
authored at least 147 papers
between 1983 and 2024.
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Bibliography
2024
Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, October, 2024
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern Classifier.
IEICE Trans. Electron., 2024
IEICE Trans. Electron., 2024
REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night.
IEICE Trans. Electron., 2024
Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers.
Proceedings of the IEEE International Memory Workshop, 2024
2023
Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM.
IEICE Trans. Electron., July, 2023
Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance.
Proceedings of the IEEE International Memory Workshop, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation.
Proceedings of the IEEE International Memory Workshop, 2022
Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM.
Proceedings of the IEEE International Memory Workshop, 2022
2021
Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory.
Proceedings of the IEEE International Memory Workshop, 2021
2020
IEEE J. Solid State Circuits, 2020
Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing.
IEEE J. Solid State Circuits, 2020
Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs).
IEICE Trans. Electron., 2020
System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs.
IEICE Trans. Electron., 2020
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories.
IEEE J. Solid State Circuits, 2019
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage.
Integr., 2019
Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaOx-based ReRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Parallel Product-Sum Operation Neuromorphic Systems with 4-bit Ferroelectric FET Synapses.
Proceedings of the 49th European Solid-State Device Research Conference, 2019
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Write and Read Frequency-Based Word-Line Batch V<sub>TH</sub> Modulation for 2-D and 3-D-TLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2018
Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test.
IEICE Trans. Electron., 2018
Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size.
IEICE Trans. Electron., 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proc. IEEE, 2017
Int. J. Biomed. Imaging, 2017
Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs.
IEICE Trans. Electron., 2017
0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive.
IEEE Trans. Very Large Scale Integr. Syst., 2016
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Design guidelines of storage class memory/flash hybrid solid-state drive considering system architecture, algorithm and workload characteristic.
IEEE Trans. Consumer Electron., 2016
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
IEEE J. Solid State Circuits, 2016
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories.
IEEE J. Solid State Circuits, 2016
Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications.
IEEE J. Solid State Circuits, 2016
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths.
IEICE Trans. Electron., 2016
Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 3D Flash Memories, 2016
2015
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs).
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories.
IEICE Trans. Electron., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten.
Proceedings of the Symposium on VLSI Circuits, 2015
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory.
Proceedings of the Symposium on VLSI Circuits, 2015
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance.
IEICE Trans. Electron., 2014
A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories.
IEICE Trans. Electron., 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Hybrid solid-state storage system with storage class memory and NAND flash memory for big-data application.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs).
IEEE J. Solid State Circuits, 2013
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy.
IEEE J. Solid State Circuits, 2013
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2012
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming.
IEEE J. Solid State Circuits, 2012
NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD.
IEEE J. Solid State Circuits, 2012
Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive.
IEICE Trans. Electron., 2012
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor.
IEICE Trans. Electron., 2012
Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs).
IEICE Electron. Express, 2012
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression.
Proceedings of the Symposium on VLSI Circuits, 2012
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 0.5 V Operation V <sub>TH</sub> Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems.
IEEE J. Solid State Circuits, 2011
Improvement of Read Margin and Its Distribution by V<sub>TH</sub> Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection.
IEEE J. Solid State Circuits, 2011
1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.
IEEE J. Solid State Circuits, 2011
Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell <i>V</i><sub>TH</sub> Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs).
IEICE Trans. Electron., 2011
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives.
IEEE J. Solid State Circuits, 2010
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.
IEICE Trans. Electron., 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD).
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2007
A 56-nm CMOS 99-mm<sup>2</sup> 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput.
IEEE J. Solid State Circuits, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
2001
A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories.
IEEE J. Solid State Circuits, 2001
2000
IEEE J. Solid State Circuits, 2000
1999
A negative V<sub>th</sub> cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
1998
A multipage cell architecture for high-speed programming multilevel NAND flash memories.
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
1996
A double-level-V<sub>th</sub> select gate array architecture for multilevel NAND flash memories.
IEEE J. Solid State Circuits, 1996
1983
Design Considerations for an Information Query Computer.
Proceedings of the Advanced Database Machine Architecture, 1983