Ken Shin

According to our database, Ken Shin authored at least 7 papers between 1995 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.

Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor.

Youngmin Shin, Ken Shin, Prashant Kenkare, Rajesh Kashyap, Hoi-Jin Lee, Dongjoo Seo, Brian Millar, Yohan Kwon, Ravi Iyengar, Min-Su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Seung Ho Hwang

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Scan-controlled pulse flip-flops for mobile application processors.

Min-Su Kim, Hyoungwook Lee, Jin-Soo Park, Chunghee Kim, Juhyun Kang, Ken Shin, Emil Kagramanyan, Gunok Jung, Ukrae Cho, Youngmin Shin, Jae-Cheol Son

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2000

A third-generation SPARC V9 64-b microprocessor.

Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You

IEEE J. Solid State Circuits, 2000

1998

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.

Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino

IEEE J. Solid State Circuits, 1998

1995

A 64-b microprocessor with multimedia support.

Lavi Lev, Andy Charnas, Marc Tremblay, Alexander Dalal, Bruce A. Frederick, Chakra R. Srivatsa, David Greenhill, Dennis L. Wendell, Duy Dinh Pham, Eric Anderson, Hemraj K. Hingarh, Inayat Razzack, James M. Kaku, Ken Shin, Marc E. Levitt, Michael Allen, Philip A. Ferolito, Richard L. Bartolotti, Robert K. Yu, Ronald J. Melanson, Shailesh I. Shah, Sophie Nguyen, Sundari S. Mitra, Vinita Reddy, Vidyasagar Ganesan, Willem J. de Lange

IEEE J. Solid State Circuits, November, 1995

A three dimensional register file for superscalar processors.

Marc Tremblay, Bill Joy, Ken Shin

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995