Ken Nakamura

According to our database1, Ken Nakamura authored at least 31 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Decoding Algorithm Correcting Single-Insertion Plus Single-Deletion for Non-binary Quantum Codes.
CoRR, 2024

2023
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture.
IEICE Trans. Electron., June, 2023

A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming.
IEICE Trans. Inf. Syst., 2023

High-definition technology of AI inference scheme for object detection on edge/terminal.
IEICE Electron. Express, 2023

2022
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders.
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022

OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021
High-definition object detection technology based on AI inference scheme and its implementation.
IEICE Electron. Express, 2021

2020
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.
IEICE Trans. Electron., 2020

MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2019
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An MMT Module for 4K/120fps Temporally Scalable Video.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control.
Proceedings of the 2019 IEEE Global Communications Conference, 2019

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations.
IEEE Trans. Consumer Electron., 2018

An HEVC real-time encoding system with high quality HDR color representations.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2015
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability.
Proceedings of the Symposium on VLSI Circuits, 2015

Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2012
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures.
IEICE Trans. Electron., 2012

2008
A Flexible Video CODEC System for Super High Resolution Video.
IEICE Trans. Inf. Syst., 2008

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV.
IEICE Trans. Inf. Syst., 2008

2007
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2004
Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Scalable architecture for use in an over-HDTV real-time codec system for multiresolution video.
Proceedings of the Visual Communications and Image Processing 2003, 2003

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.
Proceedings of the 2003 Design, 2003

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2000
Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System.
Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000

1997
Interactive Support for Decision Making.
Proceedings of the Design of Computing Systems: Social and Ergonomic Considerations, 1997

1995
Neuro-aided guidance system for optimum desulphurization treatment in torpedo cars.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995


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