Ken Mai
Orcid: 0000-0002-9096-8757
According to our database1,
Ken Mai
authored at least 76 papers
between 1998 and 2024.
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Bibliography
2024
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 10.33 μJ/encryption Homomorphic Encryption Engine in 28nm CMOS with 4096-degree 109-bit Polynomials for Resource-Constrained IoT Clients.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
2021
Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
2019
J. Parallel Distributed Comput., 2019
An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming.
CoRR, 2018
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory.
CoRR, 2018
A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
2017
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
IEEE Micro, 2016
Proceedings of the IEEE International Conference on RFID Technology and Applications, 2016
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IACR Cryptol. ePrint Arch., 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states.
Proceedings of the 2013 IEEE International Test Conference, 2013
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
2010
Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems.
Proc. IEEE, 2010
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the HOST 2010, 2010
Proceedings of the HOST 2010, 2010
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses.
Proceedings of the HOST 2010, 2010
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
Proceedings of the 47th Design Automation Conference, 2010
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Proc. IEEE, 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
2005
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005
2001
2000
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000
1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
1998
IEEE J. Solid State Circuits, 1998