Ken-ichi Yamaguchi
Orcid: 0009-0001-3790-0593
According to our database1,
Ken-ichi Yamaguchi
authored at least 9 papers
between 2001 and 2024.
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Bibliography
2024
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements.
J. Electron. Test., August, 2024
Proceedings of the 28th International Conference on Evaluation and Assessment in Software Engineering, 2024
2019
IEICE Trans. Inf. Syst., 2019
2017
Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests.
IEICE Trans. Inf. Syst., 2017
Proceedings of the 21st International Conference on Principles of Distributed Systems, 2017
2005
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Trans. Inf. Syst., 2005
2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2002
Subspace identification for continuous-time stochastic systems via distribution-based approach.
Autom., 2002
2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001