Kejie Huang
Orcid: 0000-0003-3722-9979
According to our database1,
Kejie Huang
authored at least 71 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-Based Cryptography.
ACM Trans. Reconfigurable Technol. Syst., December, 2024
Bridging partial-gated convolution with transformer for smooth-variation image inpainting.
Multim. Tools Appl., September, 2024
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024
ACM Trans. Reconfigurable Technol. Syst., March, 2024
A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
HTCNN: High-Throughput Batch CNN Inference with Homomorphic Encryption for Edge Computing.
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
CoRR, 2024
CoRR, 2024
CAAI Trans. Intell. Technol., 2024
Tetris-SDK: Efficient Convolution Layer Mapping with Adaptive Windows for Fast In Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Ground-Guided Conditional Pixel Synthesizer for Height-based Satellite Imagery Super-Resolution.
Proceedings of the International Joint Conference on Neural Networks, 2024
Automated Detection of Type II Focal Cortical Dysplasia Guided by Low-Density Electroencephalogram.
Proceedings of the Workshops at the 32nd International Conference on Case-Based Reasoning (ICCBR-WS 2024) co-located with the 32nd International Conference on Case-Based Reasoning (ICCBR 2024), 2024
A Folded Computation-in-Memory Accelerator for Fast Polynomial Multiplication in BIKE.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024
2023
J. Vis. Commun. Image Represent., December, 2023
A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
Continuous Volumetric Convolution Network With Self-Learning Kernels for Point Clouds.
IEEE Trans. Consumer Electron., May, 2023
Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by Phase-Change Memory Materials.
Adv. Intell. Syst., March, 2023
IEEE Trans. Multim., 2023
MsVRL: Self-Supervised Multiscale Visual Representation Learning via Cross-Level Consistency for Medical Image Segmentation.
IEEE Trans. Medical Imaging, 2023
Appl. Intell., 2023
TIRDet: Mono-Modality Thermal InfraRed Object Detection Based on Prior Thermal-To-Visible Translation.
Proceedings of the 31st ACM International Conference on Multimedia, 2023
Taming Vector-Wise Quantization for Wide-Range Image Blending with Smooth Transition.
Proceedings of the 1st International Workshop on Multimedia Content Generation and Evaluation: New Methods and Practice, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
2022
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Netw. Sci. Eng., 2022
IEEE Trans. Circuits Syst. Video Technol., 2022
A Customized NoC Architecture to Enable Highly Localized Computing-on-the-Move DNN Dataflow.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Int. J. Intell. Transp. Syst. Res., 2022
2021
IEEE Trans. Multim., 2021
Foreground-Background Parallel Compression With Residual Encoding for Surveillance Video.
IEEE Trans. Circuits Syst. Video Technol., 2021
Hierarchy Graph Convolution Network and Tree Classification for Epileptic Detection on Electroencephalography Signals.
IEEE Trans. Cogn. Dev. Syst., 2021
GLocal: Global Graph Reasoning and Local Structure Transfer for Person Image Generation.
CoRR, 2021
Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing.
CoRR, 2021
An Ultra Fast Low Power Convolutional Neural Network Image Sensor with Pixel-level Computing.
CoRR, 2021
A Low Power In-Memory Multiplication andAccumulation Array with Modified Radix-4 Inputand Canonical Signed Digit Weights.
CoRR, 2021
Biomed. Signal Process. Control., 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
C2F-FWN: Coarse-to-Fine Flow Warping Network for Spatial-Temporal Consistent Motion Transfer.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
An 8-bit In Resistive Memory Computing Core with Regulated Passive Neuron and Bit Line Weight Mapping.
CoRR, 2020
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2020
A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes.
Proceedings of the International SoC Design Conference, 2020
SNEQ: Semi-Supervised Attributed Network Embedding with Attention-Based Quantisation.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020
2019
Appearance Composing GAN: A General Method for Appearance-Controllable Human Video Motion Transfer.
CoRR, 2019
ECG Authentication Method Based on Parallel Multi-Scale One-Dimensional Residual Network With Center and Margin Loss.
IEEE Access, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
2018
A Two-Step Sensing Circuit for the Hysteresis Loop Selector-Based Resistive Non-Volatile Memory Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Accurate iris center localization method using facial landmark, snakuscule, circle fitting and binary connected component.
Multim. Tools Appl., 2018
Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computing.
J. Parallel Distributed Comput., 2018
2017
Power-line interference suppression in electrocardiogram using Recurrent Neural Networks.
Proceedings of the 10th International Congress on Image and Signal Processing, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
2012
Artificial neuron with somatic and axonal computation units: Mathematical and neuromorphic models of persistent firing neurons.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
2011
Proceedings of the Neural Information Processing - 18th International Conference, 2011