Keji Zhou
Orcid: 0000-0002-3078-4542
According to our database1,
Keji Zhou
authored at least 17 papers
between 2016 and 2024.
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Bibliography
2024
A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
2023
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
2022
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications.
Microelectron. J., 2022
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices.
Microelectron. J., 2022
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Toward Practical Temporal Diversity Coherent Combining Based Variable Data-Rate Free Space Optical Communication Systems.
IEEE Access, 2022
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.
IEEE J. Solid State Circuits, 2021
2020
Toward Practical Digital Phase Alignment for Coherent Beam Combining in Multi-Aperture Free Space Coherent Optical Receivers.
IEEE Access, 2020
2019
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2016
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2016