Keizo Kinoshita

According to our database1, Keizo Kinoshita authored at least 12 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Fingertip-Size Optical Module, "Optical I/O Core", and Its Application in FPGA.
IEICE Trans. Electron., 2019

2017
High-performance silicon photonics platform for low-power photonic integrated circuits.
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Resonant Wavelength Variation Modelling for Microring Resonators based on Fabrication Deviation Analysis.
Proceedings of the European Conference on Optical Communication, 2017

2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015

2014
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.
IEEE J. Solid State Circuits, June, 2013

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 3.14 um<sup>2</sup> 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Challenges for non-volatile memory & logic manufacturing utilizing magnetic tunnel junction on 300 mm wafer.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2009


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