Keith A. Campbell
Orcid: 0000-0002-3610-5256
According to our database1,
Keith A. Campbell
authored at least 11 papers
between 2015 and 2019.
Collaborative distances:
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Bibliography
2019
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
PhD thesis, 2017
Integr., 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles.
Proceedings of the 52nd Annual Design Automation Conference, 2015