Keith A. Bowman
Orcid: 0000-0002-7638-9783
According to our database1,
Keith A. Bowman
authored at least 67 papers
between 1999 and 2024.
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Bibliography
2024
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
IEEE J. Solid State Circuits, 2021
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor.
IEEE J. Solid State Circuits, 2021
Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ Processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2018
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication.
J. Signal Process. Syst., 2016
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range.
IEEE J. Solid State Circuits, 2016
2015
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors.
Proceedings of the 2014 International Test Conference, 2014
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.
IEEE J. Solid State Circuits, 2013
IEEE Des. Test, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Total power-optimal pipelining and parallel processing under process variations in nanometer technology.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2002
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration.
IEEE J. Solid State Circuits, 2002
2001
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst., 2001
Impact of within-die parameter fluctuations on future maximum clock frequency distributions.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance.
IEEE J. Solid State Circuits, 2000
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1999