Keisuke Okada

According to our database, Keisuke Okada authored at least 10 papers between 1990 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Exploiting MUSIC model to solve cold-start user problem in content-based music recommender systems.

Keisuke Okada, Manami Kanamaru, Tan Phan-Xuan, Eiji Kamioka

Intell. Decis. Technol., 2021

Five-Factor Musical Preference Prediction for Solving New User Cold-Start Problem in Content-Based Music Recommender System.

Keisuke Okada, Tan Phan-Xuan, Eiji Kamioka

Proceedings of the 12th International Conference on Information, 2021

1997

A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode.

Kazuya Yamanaka, Sumitaka Takeuchi, Shuji Murakami, Masayuki Koyama, Jun Ido, Takashi Fujiwara, Susumu Hirano, Keisuke Okada, Tadashi Sumi

IEEE J. Solid State Circuits, 1997

A high performance FIR filter dedicated to digital video transmission.

Shun Morikawa, Keisuke Okada, Sumitaka Takeuchi, Isao Shirakawa

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995

A design of high-performance multiplier for digital video transmission.

Keisuke Okada, Shun Morikawa, Isao Shirakawa, Sumitaka Takeuchi

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A 10 bit 20 MS/s 3 V supply CMOS A/D converter.

Masao Ito, Takahiro Miki, Shiro Hosotani, Toshio Kumamoto, Yukihiro Yamashita, Masaki Kijima, Takashi Okuda, Keisuke Okada

IEEE J. Solid State Circuits, December, 1994

A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter.

Takahiro Miki, Hiroyuki Kouno, Toshio Kumamoto, Yasushi Kinoshita, Takayuki Igarashi, Keisuke Okada

IEEE J. Solid State Circuits, April, 1994

1991

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano

IEEE J. Solid State Circuits, November, 1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano

IEEE J. Solid State Circuits, April, 1991

1990

A 30-MHz mixed analog/digital signal processor.

Sumitaka Takeuchi, Hiroyuki Kouno, Yoshinori Hayashi, Atsushi Maeda, Keisuke Okada, Nobuharu Yazawa

IEEE J. Solid State Circuits, December, 1990