Keishi Sakanushi

According to our database¹, Keishi Sakanushi authored at least 36 papers between 1998 and 2013.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2013

Electronic triage system for continuously monitoring casualties at disaster scenes.

[BibT_eX]

[DOI]

J. Ambient Intell. Humaniz. Comput., 2013

2012

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

On-chip Communication Buffer Architecture Optimization Considering Bus Width.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

2011

Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Automated architecture exploration for low energy reconfigurable AGU.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

Biological information sensing technologies for medical, health care, and wellness applications.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Electronic Triage System: Casualties Monitoring System in the Disaster Scene.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on P2P, 2011

2010

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Two-stage configurable decoder model for multiple forward error correction standards.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

2009

Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2007

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Block-Floating-Point Processor for Rapid Application Development.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2007

A low power VLIW processor generation method by means of extracting non-redundant activation conditions.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Pack instruction generation for media pUsing multi-valued decision diagram.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Enabling RTOS simulation modeling in a system level design language.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

S-sequence: a new floorplan representation method preserving room abutment relationships.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Architecture-Level Performance Estimation for IP-Based Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Synthesizable HDL generation method for configurable VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Code Selection Method for SIMD Processors with PACK Instructions.

[BibT_eX]

[DOI]

Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Recognition of Floorplan by Parametric BSG for Reuse of Layout Design.

[BibT_eX]

[DOI]

Keishi Sakanushi

Zhonglin Wu

Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

An improved method of convex-shaped block packing based on sequence-pair [VLSI layout].

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

1998

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.

[BibT_eX]

[DOI]

Keishi Sakanushi

Shigetoshi Nakatake

Yoji Kajitani

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Keishi Sakanushi

Timeline

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