Keiji Yoshida

According to our database1, Keiji Yoshida authored at least 29 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A design methodology for SAR ADC optimal redundancy bit.
IEICE Electron. Express, 2014

2013
Low Phase Noise 14-Bit Digitally Controlled CMOS Quadrature Ring Oscillator.
IEICE Trans. Electron., 2013

60 GHz Millimeter-Wave CMOS Integrated On-Chip Open Loop Resonator Bandpass Filters on Patterned Ground Shields.
IEICE Trans. Electron., 2013

The methods of maintaining Low frequency stability in FBAR based cross-coupled VCO design.
IEICE Electron. Express, 2013

A low phase noise FBAR based multiband VCO design.
IEICE Electron. Express, 2013

A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system.
IEICE Electron. Express, 2013

A 5-9 GHz CMOS Ultra-wideband power amplifier design using load-pull.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
A Wide Range CMOS Power Amplifier with Improved Group Delay Variation and Gain Flatness for UWB Transmitters.
IEICE Trans. Electron., 2012

CPW-fed slot antenna for UWB short-range impulse radar systems.
IEICE Electron. Express, 2012

Design of a compact size UWB planar antenna with WiMAX band rejection.
IEICE Electron. Express, 2012

High-Q SWCPL for CMOS millimeter-wave technology.
IEICE Electron. Express, 2012

A novel high-precision DAC utilizing tribonacci series.
IEICE Electron. Express, 2012

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator.
IEICE Electron. Express, 2012

Balun with passband characteristic for ultra-wideband (UWB) impulse radio transmitter.
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012

A small die area and high linearity 10-bit capacitive three-level DAC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor.
Microelectron. J., 2011

A Wide Tuning Range CMOS Quadrature Ring Oscillator with Improved FoM for Inductorless Reconfigurable PLL.
IEICE Trans. Electron., 2011

A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS.
IEICE Electron. Express, 2011

2010
High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique.
IEEE Trans. Consumer Electron., 2010

Modeling of Non-linearity in Digitally Controlled Oscillator in 0.18 µm CMOS Technology.
IEICE Trans. Electron., 2010

Low Phase Noise, 18 kHz Frequency Tuning Step, 5 GHz, 15 bit Digitally Controlled Oscillator in 0.18 µm CMOS Technology.
IEICE Trans. Electron., 2010

Design of high linearity low flicker noise 5.2 GHz down-conversion mixer for direct conversion receiver.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Development of low power DAC with pseudo Fibonacci sequence.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

A low flicker noise, highly linear, direct conversion receiver for 5GHz wireless LAN.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
Design of 5 GHz-Band Power Amplifier with On-Chip Matching Circuits Using CPW Impedance (<i>K</i>) Inverters.
IEICE Trans. Electron., 2008

2006
Design and Verification of On-Chip Impedance-Matching Circuit Using Transmission-Line Theory for 2.4 GHz-Band Wireless Receiver Front-End.
IEICE Trans. Electron., 2006

Design of a Miniaturized Superconducting Bandpass Filter by Evaluating the Kinetic Inductance in the <i>K</i>-Inverter.
IEICE Trans. Electron., 2006

2005
Electrically Small Antennas with Miniaturized Impedance Matching Circuits for Semiconductor Amplifiers.
IEICE Trans. Electron., 2005


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