Keiji Tatani

Orcid: 0000-0003-1685-2200

According to our database1, Keiji Tatani authored at least 5 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2022
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2019
A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture.
IEEE J. Solid State Circuits, 2018

A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC.
IEEE J. Solid State Circuits, 2018

A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


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