Keiji Kimura

According to our database, Keiji Kimura authored at least 70 papers between 1988 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Engineering systems analysis of mobility in Odawara city: New transportation services impacts on community engagement.

Keiji Kimura, Bryan R. Moser

Syst. Eng., May, 2024

2023

Lightweight Histological Tumor Classification Using a Joint Sparsity-Quantization Aware Training Framework.

Dina Aboutahoun, Rami Zewail, Keiji Kimura, Mostafa I. Soliman

IEEE Access, 2023

Parallel Verification in RISC-V Secure Boot.

Akihiro Saiki, Yu Omori, Keiji Kimura

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Cross-Domain Few-Shot Sparse-Quantization Aware Learning for Lymphoblast Detection in Blood Smear Images.

Dina Aboutahoun, Rami Zewail, Keiji Kimura, Mostafa I. Soliman

Proceedings of the Pattern Recognition - 7th Asian Conference, 2023

2022

Data stream clustering for low-cost machines.

Christophe Cérin, Keiji Kimura, Mamadou Sow

J. Parallel Distributed Comput., 2022

Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator.

Yu Omori, Keiji Kimura

IEEE Comput. Archit. Lett., 2022

Accelerating Data Dependence Profiling Through Abstract Interpretation of Loop Instructions.

Mostafa M. Abbas, Mostafa I. Soliman, Sherif I. Rabia, Keiji Kimura, Ahmed El-Mahdy

IEEE Access, 2022

Lightweight Array Contraction by Trace-Based Polyhedral Analysis.

Hugo Thievenaz, Keiji Kimura, Christophe Alias

Proceedings of the High Performance Computing. ISC High Performance 2022 International Workshops - Hamburg, Germany, May 29, 2022

Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler.

Tohma Kawasumi, Yuta Tsumura, Hiroki Mikami, Tomoya Yoshikawa, Takero Hosomi, Shingo Oidate, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2022

2021

Durable Queue Implementations Built on a Formally Defined Strand Persistency Model.

Jixin Han, Keiji Kimura

J. Inf. Process., 2021

Non-Volatile Main Memory Emulator for Embedded Systems Employing Three NVMM Behaviour Models.

Yu Omori, Keiji Kimura

IEICE Trans. Inf. Syst., 2021

Secure Image Inference Using Pairwise Activation Functions.

Jonas T. Agyepong, Mostafa Soliman, Yasutaka Wada, Keiji Kimura, Ahmed El-Mahdy

IEEE Access, 2021

OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper).

Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi

Proceedings of the IEEE/ACM Programming Environments for Heterogeneous Computing, 2021

Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores.

Birk Martin Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2021

Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set.

Jixin Han, Tomofumi Yuki, Michelle Mills Strout, Dan Umeda, Hironori Kasahara, Keiji Kimura

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020

Compiler-support for Critical Data Persistence in NVM.

Reem Elkhouly, Mohammad A. Alshboul, Akihiro Hayashi, Yan Solihin, Keiji Kimura

ACM Trans. Archit. Code Optim., 2020

Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler.

Yoshitake Oki, Yuto Abe, Kazuki Yamamoto, Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

IEICE Trans. Electron., 2020

Compiler Software Coherent Control for Embedded High Performance Multicore.

Boma A. Adhi, Tomoya Kashimata, Ken Takahashi, Keiji Kimura, Hironori Kasahara

IEICE Trans. Electron., 2020

Scalable and Fast Lazy Persistency on GPUs.

Ardhi Wiratama Baskara Yudha, Keiji Kimura, Huiyang Zhou, Yan Solihin

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

2019

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory.

Mohammad A. Alshboul, Hussein Elnawawy, Reem Elkhouly, Keiji Kimura, James Tuck, Yan Solihin

ACM Trans. Archit. Code Optim., 2019

Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications.

Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

Proceedings of the 9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2019

Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection.

Yu Omori, Keiji Kimura

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Performance of Static and Dynamic Task Scheduling for Real-Time Engine Control System on Embedded Multicore Processor.

Yoshitake Oki, Hiroki Mikami, Hikaru Nishida, Dan Umeda, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2019

Fast and Highly Optimizing Separate Compilation for Automatic Parallelization.

Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2018

Minimization of Akaike's information criterion in linear regression analysis via mixed integer nonlinear program.

Keiji Kimura, Hayato Waki

Optim. Methods Softw., 2018

Message from the CAP Organizing Committee.

Cristina Seceleanu, Keiji Kimura

Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018

2017

Application of mixed integer quadratic program to shortest vector problems.

Keiji Kimura, Hayato Waki, Masaya Yasuda

JSIAM Lett., 2017

Software Cache Coherent Control by Parallelizing Compiler.

Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2017

Multicore Cache Coherence Control by a Parallelizing Compiler.

Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa, Yohei Kishimoto, Masayoshi Mase

Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

A Mixed Integer Quadratic Formulation for the Shortest Vector Problem.

Keiji Kimura, Hayato Waki

Proceedings of the Mathematical Modelling for Next-Generation Cryptography: CREST Crypto-Math Project, 2017

2016

Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler.

Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara

J. Inf. Process., 2016

If-Conversion Optimization using Neuro Evolution of Augmenting Topologies.

Reem Elkhouly, Keiji Kimura, Ahmed El-Mahdy

CoRR, 2016

Reducing parallelizing compilation time by removing redundant analysis.

Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, Hironori Kasahara

Proceedings of the 3rd International Workshop on Software Engineering for Parallel Systems, 2016

Architecture Design for the Environmental Monitoring System over the Winter Season.

Koichiro Yamashita, Takahisa Suzuki, Hongchun Li, Chen Ao, Yi Xu, Jun Tian, Keiji Kimura, Hironori Kasahara

Proceedings of the 14th ACM International Symposium on Mobility Management and Wireless Access, 2016

2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores.

Lau Phi Tuong, Keiji Kimura

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Accelerating Multicore Architecture Simulation Using Application Profile.

Keiji Kimura, Gakuho Taguchi, Hironori Kasahara

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Automatic Local Memory Management for Multicores Having Global Address Space.

Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2016

Mixed Integer Nonlinear Program for Minimization of Akaike's Information Criterion.

Keiji Kimura, Hayato Waki

Proceedings of the Mathematical Software - ICMS 2016, 2016

An Android Systrace Extension for Tracing Wakelocks.

Bui Duc Binh, Keiji Kimura

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015

Annotatable systrace: an extended Linux ftrace for tracing a parallelized program.

Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara

Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

Multigrain Parallelization for Model-Based Design Applications Using the OSCAR Compiler.

Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2015

Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers.

Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2015

2014

Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores.

Tomohiro Hirano, Hideo Yamamoto, Shuhei Iizuka, Kohei Muto, Takashi Goto, Tamami Wake, Hiroki Mikami, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2014

2013

Reconciling application power control and operating systems for optimal power and performance.

Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

OSCAR Compiler Controlled Multicore Power Reduction on Android Platform.

Hideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2013

Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler.

Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

Automatic parallelization, performance predictability and power control for mobile-applications.

Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara

Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

2012

Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler.

Yasir I. M. Al-Dosary, Keiji Kimura, Hironori Kasahara, Seinosuke Narita

Int. J. Intell. Games Simul., 2012

2011

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.

Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Trans. High Perform. Embed. Archit. Compil., 2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

IEICE Trans. Electron., 2011

Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore.

Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.

Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores.

Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2010

A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers.

Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2009

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme.

Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara

Proceedings of the ICPP 2009, 2009

2008

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.

Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEEE J. Solid State Circuits, 2008

Power-Aware Compiler Controllable Chip Multiprocessor.

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEICE Trans. Electron., 2008

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API.

Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Software-cooperative power-efficient heterogeneous multi-core for media processing.

Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.

Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

Compiler Control Power Saving Scheme for Multi Core Processors.

Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2005

Performance Evaluation of Compiler Controlled Power Saving Scheme.

Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Multigrain parallel processing on compiler cooperative chip multiprocessor.

Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara

Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005

2004

Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers.

Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for High Performance Computing, 2004

2003

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP.

Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara

Int. J. Parallel Program., 2003

2002

Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler.

Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka, Keiji Kimura, Hiroki Kaminaga, Hirofumi Nakano, Kouhei Nagasawa, Akiko Murai, Hiroki Itagaki, Jun Shirako

Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

1993

Detection of small cracks in the chain of a trolley conveyor with an infrared camera.

Hajime Yamashina, Susumu Okumura, Keiji Kimura

J. Intell. Manuf., 1993

1988

CD-ROM System Based on the NEWS Workstation.

Keiji Kimura, Akihide Demura, Tatsuya Igarashi, Yukio Takeyari

Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988