Keiichi Kushida

According to our database1, Keiichi Kushida authored at least 16 papers between 2002 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.
IEEE J. Solid State Circuits, 2014

2012
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.
Proceedings of the Symposium on VLSI Circuits, 2012

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.
IEEE J. Solid State Circuits, 2011

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.
IEEE J. Solid State Circuits, 2010

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-k metal-gate CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 0.7 V Single-Supply SRAM With 0.495 µm<sup>2</sup> Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme.
IEEE J. Solid State Circuits, 2009

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
A low leakage SRAM macro with replica cell biasing scheme.
IEEE J. Solid State Circuits, 2006

2005
DFT techniques for memory macro with built-in ECC.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2002
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002


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