Keiichi Kushida

According to our database, Keiichi Kushida authored at least 16 papers between 2002 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.

Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa

IEEE J. Solid State Circuits, 2014

2012

A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the Symposium on VLSI Circuits, 2012

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2011

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.

Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2010

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm² cell in 32nm high-k metal-gate CMOS.

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 0.7 V Single-Supply SRAM With 0.495 µm² Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme.

Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2009

A process-variation-tolerant dual-power-supply SRAM with 0.179µm² Cell in 40nm CMOS using level-programmable wordline driver.

Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation.

Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka

Proceedings of the 2008 IEEE International Test Conference, 2008

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell.

Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Akihito Tohata, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

A low leakage SRAM macro with replica cell biasing scheme.

Yasuhisa Takeyama, Hiroyuki Otake, Osamu Hirabayashi, Keiichi Kushida, Nobuaki Otsuka

IEEE J. Solid State Circuits, 2006

2005

DFT techniques for memory macro with built-in ECC.

Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2002

DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.

Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002