Keiichi Koike
According to our database1,
Keiichi Koike
authored at least 5 papers
between 1993 and 2010.
Collaborative distances:
Collaborative distances:
Timeline
1994
1996
1998
2000
2002
2004
2006
2008
2010
0
1
2
3
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
1999
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design.
IEEE J. Solid State Circuits, 1999
1998
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing.
IEEE J. Solid State Circuits, 1998
1993
A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter.
IEEE J. Solid State Circuits, April, 1993
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.
Proceedings of the Algorithmic Aspects of VLSI Layout, 1993