Kei-Yong Khoo

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Sequential equivalence checking of clock-gated circuits.

[BibT_eX]

[DOI]

Yu-Yun Dai

Robert K. Brayton

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contest.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2008

Improving Constant-Coefficient Multiplier Verification by Partial Product Identification.

[BibT_eX]

[DOI]

Chao-Yue Lai

Chung-Yang Huang

Proceedings of the Design, Automation and Test in Europe, 2008

2006

Formal Verifications in Modern Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

Efficient VLSI implementation of N/N integer division.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

Optimal joint module-selection and retiming with carry-save representation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2001

DUNE-a multilayer gridless routing system.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Design of optimal hybrid form FIR filter.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Via design rule consideration in multilayer maze routing algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

DUNE: a multi-layer gridless routing system with wire planning.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Joint module selection and retiming with carry-save representation.

[BibT_eX]

[DOI]

Proceedings of the 10th European Signal Processing Conference, 2000

Efficient implementation of FIR filters using bit-level optimized carry-save additions.

[BibT_eX]

[DOI]

Proceedings of the 10th European Signal Processing Conference, 2000

The use of carry-save representation in joint module selection and retiming.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

VIA design rule consideration in multi-layer maze routing algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

Improved-Booth encoding for low-power multipliers.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.

[BibT_eX]

[DOI]

Chao-Liang Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Bit-level arithmetic optimization for carry-save additions.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An implicit connection graph maze routing algorithm for ECO routing.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1997

Interconnect design for deep submicron ICs.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

A programmable FIR digital filter using CSD coefficients.

[BibT_eX]

[DOI]

Alan Y. Kwentus

IEEE J. Solid State Circuits, 1996

Cycle-Based Timing Simulations Using Event-Stream.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

An efficient multilayer MCM router based on four-via routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Charge recovery on a databus.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients.

[BibT_eX]

[DOI]

Chao-Liang Chen

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Single-transistor transparent-latch clocking.

[BibT_eX]

[DOI]

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

Low Power CMOS Clock Buffer.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

An efficient 175 MHz programmable FIR digital filter.

[BibT_eX]

Alan Y. Kwentus

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

A fast multilayer general area router for MCM designs.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1991

A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem.

[BibT_eX]

[DOI]