Kei Hiraki

According to our database1, Kei Hiraki authored at least 83 papers between 1979 and 2019.

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Bibliography

2019
BJR-tree: fast skyline computation algorithm using dominance relation-based tree structure.
Int. J. Data Sci. Anal., 2019

2018
Continuous Skyline Computation Accelerator with Parallelizing Dominance Relation Calculations: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Skyline Computation for Low-Latency Image-Activated Cell Identification.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018

2017
BJR-Tree: Fast Skyline Computation Algorithm for Serendipitous Searching Problems.
Proceedings of the 2017 IEEE International Conference on Data Science and Advanced Analytics, 2017

2015
Keeping old computers alive for deeper understanding of computer architecture.
Proceedings of the Workshop on Computer Architecture Education, 2015

Efficient implementation of continuous skyline computation on a multi-core processor.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

An Optimization of Resource Arrangement for Network-on-Chip using Genetic Algorithm.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
FOLCS: A Lightweight Implementation of a Cycle-accurate NoC Simulator on FPGAs.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014

Accelerating cache coherence mechanism with speculation.
Proceedings of the 2014 International Conference on Supercomputing, 2014

2012
Using Cacheline Reuse Characteristics for Prefetcher Throttling.
IEICE Trans. Inf. Syst., 2012

Poster: The Impact of Integer Instructions in Floating Point Applications.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Abstract: Impact of Integer Instructions in Floating Point Applications.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Unified memory optimizing architecture: memory subsystem control with a unified predictor.
Proceedings of the International Conference on Supercomputing, 2012

2011
SIGMA-1.
Proceedings of the Encyclopedia of Parallel Computing, 2011

The performance of GRAPE-DR for dense matrix operations.
Proceedings of the International Conference on Computational Science, 2011

Access Map Pattern Matching for High Performance Data Cache Prefetch.
J. Instr. Level Parallelism, 2011

CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection.
Proceedings of the Second International Conference on Networking and Computing, 2011

2010
Simulating the universe on an intercontinental grid of supercomputers
CoRR, 2010

Simulating the Universe on an Intercontinental Grid.
Computer, 2010

Compressing Floating-Point Number Stream for Numerical Applications.
Proceedings of the First International Conference on Networking and Computing, 2010

2009
Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Access map pattern matching for data cache prefetch.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Performance optimization of TCP/IP over 10 gigabit ethernet by precise instrumentation.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

Effect of Parallel TCP Stream Equalizer on Real Long Fat-pipe Network.
Proceedings of The Seventh IEEE International Symposium on Networking Computing and Applications, 2008

Effect of Packet Shuffler on Parallel TCP Stream Network.
Proceedings of the Seventh International Conference on Networking (ICN 2008), 2008

CVC: The C to RTL compiler for callback-based verification model.
Proceedings of the FPL 2008, 2008

MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
GRAPE-DR: 2-Pflops massively-parallel computer with 512-core, 512-Gflops processor chips for scientific computing.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Heterogeneous Functional Units for High Speed Fault-Tolerant Execution Stage.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

GRAPE-DR Project: a combination of peta-scale computing and high-speed networking.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Flow Balancing Hardware for Parallel TCP Streams on Long Fat Pipe Network.
Proceedings of the Future Generation Communication and Networking, 2007

2006
Network Processing Hardware.
Proceedings of the Technologies for Advanced Heterogeneous Networks II, 2006

Applying recent techniques for retro games: in the case of undo function.
Proceedings of the International Conference on Advances in Computer Entertainment Technology, 2006

2005
Software SMLP Execution with Side-Effect Slice Exclusion.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

High-speed and Memory Efficient TCP Stream Scanning using FPGA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Sentinel PRE: Hoisting beyond Exception Dependency with Dynamic Deoptimization.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2004
A computer architecture education curriculum through the design and implementation of original processors using FPGAs.
Proceedings of the 2004 workshop on Computer architecture education, 2004

Inter-Layer Coordination for Parallel TCP Streams on Long Fat Pipe Networks.
Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 2004

Utilizing Dynamic Data Value Localities in Internal Variables.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004

Partial Value Number Redundancy Elimination.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Long Fat Pipe Congestion Control for Multi-Stream Data Transfer.
Proceedings of the 7th International Symposium on Parallel Architectures, 2004

Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004

Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Field Array Compression in Data Caches for Dynamically Allocated Recursive Data Structure.
Proceedings of the High Performance Computing, 5th International Symposium, 2003

Selective Optimization of Locks by Runtime Statistics and Just-in-Time Compilation.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Compression in Data Caches with Compressible Field Isolation for Recursive Data Structures.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
Data Reservoir: utilization of multi-gigabit backbone network for data-intensive research.
Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002

Highly Fault-Tolerant FPGA Processor by Degrading Strategy.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Data Reservoir: A New Approach to Data-Intensive Scientific Computation.
Proceedings of the International Symposium on Parallel Architectures, 2002

2000
Comparative study of page-based and segment-based software DSM through compiler optimization.
Proceedings of the 14th international conference on Supercomputing, 2000

1999
On the Schedulability Conditions on Partial Time Slots .
Proceedings of the 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 1999

Performance Evaluation of the MPI/MBCF with the NAS Parallel Benchmarks.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1999

Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
Implementing MPI with the Memory-Based Communication Facilities on the SSS-CORE Operating System.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1998

MBCF: A Protected and Virtualized High-Speed User-Level Memory-Based Communication Facility.
Proceedings of the 12th international conference on Supercomputing, 1998

Speculative Execution Model with Duplication.
Proceedings of the 12th international conference on Supercomputing, 1998

Supporting Software Distributed Shared Memory with an Optimizing Compiler.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1997
Efficient Implementation of Software Release Consistency on Asymmetric Distributed Shared Memory.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

Resource Management Methods for General Purpose Massively Parallel OS SSS-Core.
Proceedings of the High Performance Computing, International Symposium, 1997

An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.
Proceedings of the 11th international conference on Supercomputing, 1997

1996
Distributed Shared Memory Architecture for JUMP-1: A General-Purpose MPP Prototype.
Proceedings of the 1996 International Symposium on Parallel Architectures, 1996

1995
High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

1994
Automatic Reduction Tree Generation for Fine-Grain Parallel Architectures when Iteration Count is Unknown.
Proceedings of the Languages and Compilers for Parallel Computing, 1994

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.
Proceedings of the International Symposium on Parallel Architectures, 1994

An Architecture for Generalized Synchronization and Fast Switching.
Proceedings of the Multithreaded Computer Architecture, 1994

1993
Dynamic Switching of Coherent Cache Protocols and its Effects on Doacross Loops.
Proceedings of the 7th international conference on Supercomputing, 1993

Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor.
Proceedings of the 7th international conference on Supercomputing, 1993

1991
Sequential description and parallel execution language DFCII dataflow supercomputers.
Proceedings of the 5th international conference on Supercomputing, 1991

1990
Dataflow computer development in Japan.
Proceedings of the 4th international conference on Supercomputing, 1990

1989
Data flow language DFC: Design and implementation.
Syst. Comput. Jpn., 1989

An Architecture of a Dataflow Single Chip Processor.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

An Architectural Disgn of a Highly Parallel Dataflow Machine.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988
Efficient vector processing on dataflow supercomputer SIGMA-1.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

1987
Load scheduling schemes using inter - PE network.
Syst. Comput. Jpn., 1987

The SIGMA-1 dataflow computer.
Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow, 1987

1986
Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors.
Proceedings of the International Conference on Parallel Processing, 1986

1984
Evaluation of Associative Memory Using Parallel Chained Hashing.
IEEE Trans. Computers, 1984

An Architecture of a Data Flow Machine and Its Evaluation.
Proceedings of the COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27, 1984

1982
Design of a Lisp Machine - FLATS.
Proceedings of the 1982 ACM Symposium on LISP and Functional Programming, 1982

1979
FLATS, a Machine for Numerical, Symbolic and Associative Computing.
Proceedings of the 6th Annual Symposium on Computer Architecture, 1979


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