Kee-Won Kwon
Orcid: 0000-0003-4513-8532
According to our database1,
Kee-Won Kwon
authored at least 49 papers
between 2004 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs.
IEEE Access, 2025
2024
Proceedings of the 21st International SoC Design Conference, 2024
A Highly-Sensitive and Compact Interconnect Delay Monitoring Circuit for 3-Dimensional System Packages.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
Si Bridge With Chessboard Patterned Interconnect (CPI): Enabling High Density, High Efficiency Heterogeneous Integration.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
Highly Linear Charging/Discharging of Charge Trap FET Using Regulated Single Pulse for Neural Accelerator.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
2022
A 6.23-bit FG-based Neuromorphic Synaptic Device with Extended Input Range by Linearity Improvement.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
Proceedings of the IEEE International Conference on Big Data, 2022
2021
Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic Devices.
Proceedings of the 18th International SoC Design Conference, 2021
2020
A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth.
IEEE J. Solid State Circuits, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEICE Electron. Express, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEICE Electron. Express, 2013
A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications.
IEICE Electron. Express, 2013
A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Microelectron. J., 2010
2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2004
Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs.
IEEE J. Solid State Circuits, 2004