Kee Sup Kim

According to our database1, Kee Sup Kim authored at least 35 papers between 1990 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2014
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Early-life-failure detection using SAT-based ATPG.
Proceedings of the 2013 IEEE International Test Conference, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Thermal-aware body bias modulation for high performance mobile core.
Proceedings of the International SoC Design Conference, 2012

A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Apprentice - VTS edition: Season 4.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Holistic low power solutions for the new world.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
Panel 12C: Apprentice - VTS edition judging session.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Panel 4A: Apprentice - VTS edition: Season 3.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2009
Panel: Apprentice - VTS Edition: Season 2.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Framework for massively parallel testing at wafer and package test.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Hierarchical Test Compression for SoC Designs.
IEEE Des. Test Comput., 2008

2007
Design for Resilience to Soft Errors and Variations.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Sequential Element Design With Built-In Soft Error Resilience.
IEEE Trans. Very Large Scale Integr. Syst., 2006

XPAND: An Efficient Test Stimulus Compression Technique.
IEEE Trans. Computers, 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Soft Error Resilient System Design through Error Correction.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Combinational Logic Soft Error Correction.
Proceedings of the 2006 IEEE International Test Conference, 2006

OCI: Open Compression Interface.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim.
Computer, 2005

Logic soft errors: a major barrier to robust platform design.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

XMAX: a practical and efficient compression architecture.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

How to determine the necessity for emerging solutions.
Proceedings of the 42nd Design Automation Conference, 2005

Robust platform design in advanced VLSI technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
X-compact: an efficient response compaction technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Delay Defect Characteristics and Testing Strategies.
IEEE Des. Test Comput., 2003

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

XMAX: X-Tolerant Architecture for MAXimal Test Compression.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
DPDAT: data path direct access testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

SpeedGrade: An RTL Path Delay Fault Simulator.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1995
Partial scan flip-flop selection by use of empirical testability.
J. Electron. Test., 1995

1994
Multi-Frequency, Multi-Phase Scan Chain.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
Partial Scan Using Reverse Direction Empirical Testability.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1990
Partial Scan by Use of Empirical Testability.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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