Kedarnath J. Balakrishnan

According to our database, Kedarnath J. Balakrishnan authored at least 21 papers between 2002 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor.

Kedarnath J. Balakrishnan, Grady Giles, James Wingfield

IEEE Des. Test Comput., 2009

2008

X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors.

Seongmoon Wang, Kedarnath J. Balakrishnan, Wenlong Wei

IEEE Trans. Computers, 2008

Test Access Mechanism for Multiple Identical Cores.

Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Relationship Between Entropy and Test Data Compression.

Kedarnath J. Balakrishnan, Nur A. Touba

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

RTL Test Point Insertion to Reduce Delay Test Volume.

Kedarnath J. Balakrishnan, Lei Fang

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding.

Kedarnath J. Balakrishnan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Test cost reduction for SoC using a combined approach to test data compression and test scheduling.

Quming Zhou, Kedarnath J. Balakrishnan

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Improving Linear Test Data Compression.

Kedarnath J. Balakrishnan, Nur A. Touba

IEEE Trans. Very Large Scale Integr. Syst., 2006

PIDISC: Pattern Independent Design Independent Seed Compression Technique.

Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Efficient unknown blocking using LFSR reseeding.

Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

XWRC: externally-loaded weighted random pattern testing for input test data compression.

Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 2005 Design, 2005

Compressing Functional Tests for Microprocessors.

Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Emerging Techniques for Test Data Compression.

Kedarnath J. Balakrishnan

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Matrix-based software test data decompression for systems-on-a-chip.

Kedarnath J. Balakrishnan, Nur A. Touba

J. Syst. Archit., 2004

Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Relating entropy theory to test data compression.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 9th European Test Symposium, 2004

Re-configurable embedded core test protocol.

Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Deterministic Test Vector Decompression in Software Using Linear Operations.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Scan-Based BIST Diagnosis Using an Embedded Processor.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

Matrix-Based Test Vector Decompression Using an Embedded Processor.

Kedarnath J. Balakrishnan, Nur A. Touba

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002