Kecheng Ji

According to our database, Kecheng Ji authored at least 7 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.

Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi

Microprocess. Microsystems, 2019

2018

An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.

Kecheng Ji, Ming Ling, Longxing Shi, Jianping Pan

ACM Trans. Embed. Comput. Syst., 2018

2017

An artificial neural network model of LRU-cache misses on out-of-order embedded processors.

Kecheng Ji, Ming Ling, Yang Zhang, Longxing Shi

Microprocess. Microsystems, 2017

Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.

Kecheng Ji, Ming Ling, Longxing Shi

Microprocess. Microsystems, 2017

A mechanistic model of memory level parallelism fed with cache miss rates.

Qin Wang, Kecheng Ji, Ming Ling, Longxing Shi

Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

A trace-driven analytical model with less profiling overhead for DRAM access latencies.

Fengying Sun, Kecheng Ji, Ming Ling, Longxing Shi

Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

AFEC: An analytical framework for evaluating cache performance in out-of-order processors.

Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017