Ke Huang

Orcid: 0000-0002-1587-9877

Affiliations:
  • San Diego State University, Department of Electrical and Computer Engineering, CA, USA
  • University of Texas at Dallas, Richardson, TX, USA (2012 - 2014)
  • University of Grenoble, France (PhD 2011)
  • Joseph Fourier University, Grenoble I University, Grenoble, France, (former)


According to our database1, Ke Huang authored at least 45 papers between 2010 and 2024.

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Links

Online presence:

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Bibliography

2024
FaceSigns: Semi-fragile Watermarks for Media Authentication.
ACM Trans. Multim. Comput. Commun. Appl., November, 2024

Scalable Binary Neural Network Applications in Oblivious Inference.
ACM Trans. Embed. Comput. Syst., May, 2024

Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond.
IEEE Des. Test, 2024

Unveiling Analog Aging Trojans (ATs): Vulnerabilities and Detection Strategies.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023
AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection.
ACM Trans. Embed. Comput. Syst., March, 2023

zPROBE: Zero Peek Robustness Checks for Federated Learning.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

2022
DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Adaptive Black-box Backdoor Detection Method for Deep Neural Networks.
CoRR, 2022

FaceSigns: Semi-Fragile Neural Watermarks for Media Authentication and Countering Deepfakes.
CoRR, 2022

2021
Eco-Driving System for Connected Automated Vehicles: Multi-Objective Trajectory Optimization.
IEEE Trans. Intell. Transp. Syst., 2021

Real-Time IC Aging Prediction via On-Chip Sensors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

On the Application of Binary Neural Networks in Oblivious Inference.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2021

2019
Real-Time Prediction for IC Aging Based on Machine Learning.
IEEE Trans. Instrum. Meas., 2019

2018
Ecological Driving System for Connected/Automated Vehicles Using a Two-Stage Control Hierarchy.
IEEE Trans. Intell. Transp. Syst., 2018

Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning.
J. Electron. Test., 2018

Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing.
J. Electron. Test., 2018

AgileNet: Lightweight Dictionary-based Few-shot Learning.
CoRR, 2018

IC layout weak point effectiveness evaluation based on statistical methods.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016
Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Prognosis of NBTI aging using a machine learning scheme.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
Recycled IC Detection Based on Statistical Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models.
IEEE Des. Test, 2015

Yield prognosis for fab-to-fab product migration.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A comparative study of one-shot statistical calibration methods for analog / RF ICs.
Proceedings of the 2015 IEEE International Test Conference, 2015

Concurrent hardware Trojan detection in wireless cryptographic ICs.
Proceedings of the 2015 IEEE International Test Conference, 2015

2014
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.
Proc. IEEE, 2014

Innovative practices session 4C: Disruptive solutions in the non-digital world.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

IC laser trimming speed-up through wafer-level spatial correlation modeling.
Proceedings of the 2014 International Test Conference, 2014

Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.
Proceedings of the 2014 International Test Conference, 2014

Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Fault modeling and diagnosis for nanometric analog circuits.
Proceedings of the 2013 IEEE International Test Conference, 2013

Process monitoring through wafer-level spatial variation decomposition.
Proceedings of the 2013 IEEE International Test Conference, 2013

Counterfeit electronics: A rising threat in the semiconductor manufacturing industry.
Proceedings of the 2013 IEEE International Test Conference, 2013

Reconciling the IC test and security dichotomy.
Proceedings of the 18th IEEE European Test Symposium, 2013

On combining alternate test with spatial correlation modeling in analog/RF ICs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Multivariate statistical techniques for analog parametric test metrics estimation.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Diagnosis of Local Spot Defects in Analog Circuits.
IEEE Trans. Instrum. Meas., 2012

Spatial estimation of wafer measurement parameters using Gaussian process models.
Proceedings of the 2012 IEEE International Test Conference, 2012

Accurate estimation of analog test metrics with extreme circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Spatial correlation modeling for probe test cost reduction in RF devices.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Parametric counterfeit IC detection via Support Vector Machines.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2010
Fault diagnosis of analog circuits based on machine learning.
Proceedings of the Design, Automation and Test in Europe, 2010

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010


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