Ke Huang
Orcid: 0000-0002-1587-9877Affiliations:
- San Diego State University, Department of Electrical and Computer Engineering, CA, USA
- University of Texas at Dallas, Richardson, TX, USA (2012 - 2014)
- University of Grenoble, France (PhD 2011)
- Joseph Fourier University, Grenoble I University, Grenoble, France, (former)
According to our database1,
Ke Huang
authored at least 45 papers
between 2010 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2024
ACM Trans. Multim. Comput. Commun. Appl., November, 2024
ACM Trans. Embed. Comput. Syst., May, 2024
IEEE Des. Test, 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
2023
AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection.
ACM Trans. Embed. Comput. Syst., March, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
2022
DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
FaceSigns: Semi-Fragile Neural Watermarks for Media Authentication and Countering Deepfakes.
CoRR, 2022
2021
Eco-Driving System for Connected Automated Vehicles: Multi-Objective Trajectory Optimization.
IEEE Trans. Intell. Transp. Syst., 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2021
2019
IEEE Trans. Instrum. Meas., 2019
2018
Ecological Driving System for Connected/Automated Vehicles Using a Two-Stage Control Hierarchy.
IEEE Trans. Intell. Transp. Syst., 2018
J. Electron. Test., 2018
J. Electron. Test., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models.
IEEE Des. Test, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
2014
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.
Proc. IEEE, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 2014 International Test Conference, 2014
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.
Proceedings of the 2014 International Test Conference, 2014
Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Counterfeit electronics: A rising threat in the semiconductor manufacturing industry.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010