Kazuyoshi Yoshida

According to our database, Kazuyoshi Yoshida authored at least 3 papers between 1996 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier.

Akira Tanabe, Masaaki Soda, Yasushi Nakahara, Takao Tamura, Kazuyoshi Yoshida, Akio Furukawa

IEEE J. Solid State Circuits, 1998

1996

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.

Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda

IEEE J. Solid State Circuits, 1996

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology.

Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida

IEEE J. Solid State Circuits, 1996