Kazuyasu Fujishima

According to our database1, Kazuyasu Fujishima authored at least 22 papers between 1986 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.
IEEE J. Solid State Circuits, 2005

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.
IEEE J. Solid State Circuits, 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.
IEICE Trans. Electron., 2005

2000
High-performance embedded SOI DRAM architecture for the low-power supply.
IEEE J. Solid State Circuits, 2000

1994
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology.
IEEE J. Solid State Circuits, November, 1994

An experimental 256-Mb DRAM with boosted sense-ground scheme.
IEEE J. Solid State Circuits, November, 1994

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.
IEEE J. Solid State Circuits, April, 1994

1993
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.
IEEE Des. Test Comput., 1993

1992
A 34-ns 16-Mb DRAM with controllable voltage down-converter.
IEEE J. Solid State Circuits, July, 1992

A high-density dual-port memory cell operation and array architecture for ULSI DRAMs.
IEEE J. Solid State Circuits, April, 1992

A dual-mode sensing scheme of capacitor-coupled EEPROM cell.
IEEE J. Solid State Circuits, April, 1992

Cell-plate line connecting complementary bit-line (C<sup>3</sup>) architecture for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1992

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
A divided/shared bit-line sensing scheme for ULSI DRAM cores.
IEEE J. Solid State Circuits, April, 1991

A circuit design of intelligent cache DRAM with automatic write-back capability.
IEEE J. Solid State Circuits, April, 1991

1990
An experimental 1-Mbit cache DRAM with ECC.
IEEE J. Solid State Circuits, February, 1990

The cache DRAM architecture: a DRAM with an on-chip cache memory.
IEEE Micro, 1990

1989
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register.
IEEE J. Solid State Circuits, October, 1989

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode.
IEEE J. Solid State Circuits, February, 1989

Twisted bit-line architectures for multi-megabit DRAMs.
IEEE J. Solid State Circuits, February, 1989

A New Array Architecture for Parallel Testing in VLSI Memories.
Proceedings of the Proceedings International Test Conference 1989, 1989

1986
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
Proceedings of the Proceedings International Test Conference 1986, 1986


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