Kazuyasu Fujishima
According to our database1,
Kazuyasu Fujishima
authored at least 22 papers
between 1986 and 2005.
Collaborative distances:
Collaborative distances:
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Bibliography
2005
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.
IEEE J. Solid State Circuits, 2005
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.
IEEE J. Solid State Circuits, 2005
IEICE Trans. Electron., 2005
2000
IEEE J. Solid State Circuits, 2000
1994
IEEE J. Solid State Circuits, November, 1994
IEEE J. Solid State Circuits, November, 1994
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.
IEEE J. Solid State Circuits, April, 1994
1993
IEEE Des. Test Comput., 1993
1992
IEEE J. Solid State Circuits, July, 1992
A high-density dual-port memory cell operation and array architecture for ULSI DRAMs.
IEEE J. Solid State Circuits, April, 1992
IEEE J. Solid State Circuits, April, 1992
Cell-plate line connecting complementary bit-line (C<sup>3</sup>) architecture for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1991
IEEE J. Solid State Circuits, April, 1991
IEEE J. Solid State Circuits, April, 1991
1990
IEEE J. Solid State Circuits, February, 1990
1989
IEEE J. Solid State Circuits, October, 1989
IEEE J. Solid State Circuits, February, 1989
IEEE J. Solid State Circuits, February, 1989
Proceedings of the Proceedings International Test Conference 1989, 1989
1986
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
Proceedings of the Proceedings International Test Conference 1986, 1986