Kazuya Katsuki

According to our database, Kazuya Katsuki authored at least 6 papers between 2005 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.

Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera

IEICE Trans. Electron., 2007

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.

Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera

IEICE Trans. Electron., 2007

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.

Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.

Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.

Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A yield and speed enhancement scheme under within-die variations on 90nm LUT array.

Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005