Kazuteru Namba
Orcid: 0000-0002-8316-7281
According to our database1,
Kazuteru Namba
authored at least 79 papers
between 2001 and 2024.
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage.
IEICE Trans. Inf. Syst., 2024
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024
A Master-Slave Flip-Flop with Double-Node-Upset Self-Recovery and Soft Error Tolerance around Clock Edges.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024
2023
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023
2022
Proceedings of the 27th IEEE Pacific Rim International Symposium on Dependable Computing, 2022
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
2021
Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
2020
IEICE Trans. Inf. Syst., 2020
Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge.
IEICE Trans. Inf. Syst., 2020
Influence of Recognition Performance on Recurrent Neural Network Using Phase-Change Memory as Synapses.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020
2019
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM).
IEEE Trans. Computers, 2019
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Computers, 2018
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
2017
Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017
2016
IEEE Trans. Multi Scale Comput. Syst., 2016
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers, 2016
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems.
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
IPSJ Trans. Syst. LSI Des. Methodol., 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
2015
IEEE Trans. Computers, 2015
IEEE Trans. Computers, 2015
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion.
IEICE Trans. Inf. Syst., 2014
IEICE Trans. Inf. Syst., 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF.
IEICE Trans. Inf. Syst., 2013
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA.
IEICE Trans. Inf. Syst., 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2012
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
IEEE Trans. Computers, 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
IEICE Trans. Inf. Syst., 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEICE Trans. Inf. Syst., 2010
J. Electron. Test., 2010
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
IEICE Trans. Inf. Syst., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.
IEICE Trans. Inf. Syst., 2009
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.
IEICE Trans. Inf. Syst., 2009
IEICE Trans. Inf. Syst., 2009
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.
J. Electron. Test., 2009
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
IPSJ Trans. Syst. LSI Des. Methodol., 2008
J. Electron. Test., 2008
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings.
Syst. Comput. Jpn., 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding.
Proceedings of the 15th Asian Test Symposium, 2006
2005
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Inf. Syst., 2005
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005
2002
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2001
Syst. Comput. Jpn., 2001
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001