Kazutaka Ikegami

According to our database, Kazutaka Ikegami authored at least 10 papers between 2008 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications.

Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2017

Novel memory hierarchy with e-STT-MRAM for near-future applications.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU.

Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita

Proceedings of the Symposium on VLSI Circuits, 2014

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2012

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.

Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito

CoRR, 2011

2010

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).

Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2008

1200μm² Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application.

Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008