Kazushige Kanda

According to our database1, Kazushige Kanda authored at least 12 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface.
IEEE J. Solid State Circuits, 2023

2022

2020
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology.
IEEE J. Solid State Circuits, 2020

2019

2018

2013
A 19 nm 112.8 mm<sup>2</sup> 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
IEEE J. Solid State Circuits, 2013

2012
An Embedded DRAM Technology for High-Performance NAND Flash Memories.
IEEE J. Solid State Circuits, 2012


2008

2002
A 125-mm<sup>2</sup> 1-Gb NAND flash memory with 10-MByte/s program speed.
IEEE J. Solid State Circuits, 2002

1999
A 130-mm/<sup>2</sup>, 256-Mbit NAND flash with shallow trench isolation technology.
IEEE J. Solid State Circuits, 1999

1997
A 120-mm<sup>2</sup> 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.
IEEE J. Solid State Circuits, 1997


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