Kazushige Ayukawa

According to our database, Kazushige Ayukawa authored at least 3 papers between 1997 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2001

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.

Seiji Miura, Kazushige Ayukawa, Takao Watanabe

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

1998

An access-sequence control scheme to enhance random-access performance of embedded DRAM's.

Kazushige Ayukawa, Takao Watanabe, Susumu Narita

IEEE J. Solid State Circuits, 1998

1997

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.

Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome

IEEE J. Solid State Circuits, 1997