Kazuo Otsuga

According to our database, Kazuo Otsuga authored at least 8 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.

Takao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor.

Kazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.

Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2008

A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model.

Shinya Kajiyama, Ken'ichiro Sonoda, Kazuo Otsuga, Hideaki Kurata, Kiyoshi Ishikawa

IEICE Trans. Electron., 2008

2007

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.

Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya

IEEE J. Solid State Circuits, 2007

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories.

Kazuo Otsuga, Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi

IEICE Trans. Electron., 2007

A 126 mm² 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology.

Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Teruhiko Ito, Yoshinori Sakamoto, Masahiro Shimizu, Yoshinori Ikeda, Osamu Tsuchiya, Kazunori Furusawa

IEICE Trans. Electron., 2007

2005

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories.

Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara

IEEE J. Solid State Circuits, 2005