Kazuo Nakajima

According to our database1, Kazuo Nakajima authored at least 32 papers between 1980 and 2006.

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Bibliography

2006
An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A New Approach to Online FPGA Placement.
Proceedings of the 40th Annual Conference on Information Sciences and Systems, 2006

2003
Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems.
EURASIP J. Adv. Signal Process., 2003

Roles of funding agencies in technology-driven economic development.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A Component Architecture for FPGA-Based, DSP System Design.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2000
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
SEGRA: a very fast general area router for multichip modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays.
Discret. Appl. Math., 1999

Maximum/minimum detection by a module-based neural network with redundant architecture.
Proceedings of the International Joint Conference Neural Networks, 1999

1997
A simple and effective greedy multilayer router for MCMs.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1995
Min-cut placement with global objective functions for large scale sea-of-gates arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994
A new approach to over-the-cell channel routing with three layers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
A Reconfiguration-Based Yield Enhancement System.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
Site-specific dissection of E. coli chromosome by lambda terminase.
Nucleic Acids Res., 1992

General Circular Permutation Layout.
Math. Syst. Theory, 1992

Generation of Maximum Independent Sets of a Bipartite Graph and Maximum Cliques of a Circular-Arc Graph.
J. Algorithms, 1992

1991
Polynomial time algorithms on circular-arc overlap graphs.
Networks, 1991

A New Model for Over-The-Cell Channel Routing with Three Layers.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Crossing Minimization in Linear Embeddings of Graphs.
IEEE Trans. Computers, 1990

Efficient algorithms for finding maximum cliques of an overlap graph.
Networks, 1990

A linear time algorithm for optimal CMOS functional cell layouts.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
Exact algorithms for multilayer topological via minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

The Via Minimization Problem is NP-Complete.
IEEE Trans. Computers, 1989

Graph Bipartization and via Minimization.
SIAM J. Discret. Math., 1989

1988
An Optimal Algorithm for Finding a Maximum Independent Set of a Circular-Arc Graph.
SIAM J. Comput., 1988

1987
Via Minimization for Gridless Layouts.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
An Algorithm for Determining the Fault Diagnosability of a System.
IEEE Trans. Computers, 1986

1984
On Adaptive System Diagnosis.
IEEE Trans. Computers, 1984

1982
Complexity Results for Scheduling Tasks with Discrete Starting Times.
J. Algorithms, 1982

1980
Traffic Assistance Service System for ESS.
IEEE Trans. Commun., 1980


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