Kazuo Matsukawa
According to our database1,
Kazuo Matsukawa
authored at least 9 papers
between 2006 and 2016.
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Timeline
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2016
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
IEEE J. Solid State Circuits, 2015
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method.
Proceedings of the Symposium on VLSI Circuits, 2012
2010
IEEE J. Solid State Circuits, 2010
A 69.8 dB SNDR 3<sup>rd</sup>-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006