Kazunori Shimizu

According to our database, Kazunori Shimizu authored at least 17 papers between 1999 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Development of in vivo gene delivery methods in mice using tissue suction devices for abdominal endoscopic gene therapy.

Kazunori Shimizu, Shigeru Kawakami, Kouji Hayashi, Shingo Katano, Guangyuan Zhang, Dai Maekawa, Mitsuru Hashida, Satoshi Konishi

Proceedings of the International Symposium on Micro-NanoMechatronics and Human Science, 2012

Introducing faceted views in diversity of online novels.

Eisuke Ito, Sachio Hirokawa, Kazunori Shimizu

Proceedings of the Seventh International Conference on Digital Information Management, 2012

Frequency and Link Analysis of Online Novels Toward Social Contents Ranking.

Eisuke Ito, Kazunori Shimizu

Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

2008

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique.

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems.

Qin Liu, Seiichiro Hiratsuka, Kazunori Shimizu, Shinsuke Ushiki, Satoshi Goto, Takeshi Ikenaga

IEICE Trans. Electron., 2008

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2ⁿ).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms.

Qi Wang, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Electron., 2007

Power-efficient LDPC code decoder architecture.

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule.

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A parallel LSI architecture for LDPC decoder improving message-passing schedule.

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-throughput decoder for low-density parity-check code.

Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Memory-Efficient Accelerating Schedule for LDPC Decoder.

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving.

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

IEICE Trans. Inf. Syst., 2005

Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm.

Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Reconfigurable adaptive FEC system with interleaving.

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

1999

High-speed End Milling of Extruded Aluminum Alloys Using Articulated Robot.

Kazunori Shimizu, Shin-ichi Matsuoka, Nobuyuki Yamazaki, Yoshinari Oki

J. Robotics Mechatronics, 1999