Kazunari Kato

According to our database, Kazunari Kato authored at least 5 papers between 2009 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

Two phase clocked subthreshold adiabatic logic circuit.

Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine

IEICE Electron. Express, 2015

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic.

Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014

Two phase clocking subthreshold adiabatic logic.

Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic.

Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2009

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication.

Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine

Proceedings of the 16th IEEE International Conference on Electronics, 2009