Kazunari Inoue

According to our database, Kazunari Inoue authored at least 22 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An Embedded core of Content-based maskable CAM exploring Longest Prefix Match fashion.

Atsushi Ooka, Kazunari Inoue, Takaya Miyazawa

Proceedings of the 21st International SoC Design Conference, 2024

2019

An IoT-gateway with the information-centric communication.

Kazunari Inoue, Nozomi Kobori, Atsushi Hirota, Tetsushi Koide, Takumi Okamoto

Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019

2016

A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM.

Kazunari Inoue, Yuji Yano

Proceedings of the International SoC Design Conference, 2016

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure.

Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka

Proceedings of the 13th IEEE Annual Consumer Communications & Networking Conference, 2016

2015

High-Speed Design of Conflictless Name Lookup and Efficient Selective Cache on CCN Router.

Atsushi Ooka, Shingo Ata, Kazunari Inoue, Masayuki Murata

IEICE Trans. Commun., 2015

2014

Design of a high-speed content-centric-networking router using content addressable memory.

Atsushi Ooka, Shingo Ata, Kazunari Inoue, Masayuki Murata

Proceedings of the 2014 Proceedings IEEE INFOCOM Workshops, Toronto, ON, Canada, April 27, 2014

2013

A study on micro level traffic prediction for energy-aware routers.

Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka

ACM SIGOPS Oper. Syst. Rev., 2013

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka

IEICE Trans. Electron., 2013

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue

IEICE Trans. Commun., 2013

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving.

Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka

Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013

2012

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine.

Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka

IEICE Trans. Commun., 2012

A High-Grained Traffic Prediction for Microseconds Power Control in Energy-Aware Routers.

Sou Koyano, Shingo Ata, Ikuo Oka, Kazunari Inoue

Proceedings of the IEEE Fifth International Conference on Utility and Cloud Computing, 2012

A slice structure using the management of network traffic prediction for green IT.

Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue

Proceedings of the 13th IEEE International Conference on High Performance Switching and Routing, 2012

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application.

Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Deterministic High Density Packet-Buffer System for Low Cost Network Systems.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue

Proceedings of the IEEE 26th International Conference on Advanced Information Networking and Applications, 2012

2010

A New TCAM Architecture for Managing ACL in Routers.

Haesung Hwang, Shingo Ata, Koji Yamamoto, Kazunari Inoue, Masayuki Murata

IEICE Trans. Commun., 2010

Hardware implementation of fast forwarding engine using standard memory and dedicated circuit.

Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2005

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.

Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.

Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.

Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide

IEICE Trans. Electron., 2005

1995

A 10 Mb frame buffer memory with Z-compare and A-blend units.

Kazunari Inoue, Hisashi Nakamura, Hiroyuki Kawai

IEEE J. Solid State Circuits, December, 1995

Advances in DRAM interfaces.

Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue

IEEE Micro, 1995