Kazumasa Sunouchi

According to our database, Kazumasa Sunouchi authored at least 2 papers between 2002 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture.

Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2002

Memory design using a one-transistor gain cell on SOI.

Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

IEEE J. Solid State Circuits, 2002