Kazuhiro Hashimoto

According to our database, Kazuhiro Hashimoto authored at least 5 papers between 1991 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2013

Towards the Profitability Trend Extraction from the Board Meeting Proceedings.

Masakazu Takahashi, Kenji Kido, Kazuhiro Hashimoto

Proceedings of the 17th International Conference in Knowledge Based and Intelligent Information and Engineering Systems, 2013

2001

CPU for PlayStation 2.

Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Importance of CAD tools and methodology in high speed CPU design: invited talk.

Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto

Proceedings of ASP-DAC 2000, 2000

1999

A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder.

Masakazu Suzuoki, Ken Kutaragi, Toshiyuki Hiroi, Hidetaka Magoshi, Shin'ichi Okamoto, Masaaki Oka, Akio Ohba, Yasuyuki Yamamoto, Makoto Furuhashi, Masayoshi Tanaka, Teiji Yutaka, Toyoshi Okada, Masato Nagamatsu, Yukihiro Urakawa, Masami Funyu, Atsushi Kunimatsu, Harutaka Goto, Kazuhiro Hashimoto, Nobuhiro Ide, Hiroaki Murakami, Yukio Ohtaguro, Akira Aono

IEEE J. Solid State Circuits, 1999

1991

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology.

Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Toyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, Kenji Maeguchi

IEEE J. Solid State Circuits, April, 1991