Kazuhiko Terada

According to our database1, Kazuhiko Terada authored at least 8 papers between 1998 and 2021.

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Bibliography

2021
Distributed Deep Learning With GPU-FPGA Heterogeneous Computing.
IEEE Micro, 2021

A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation.
IEICE Trans. Commun., 2021

2020
Communication-Efficient Distributed Deep Learning with GPU-FPGA Heterogeneous Computing.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2020

2015
High-speed sorted-table search scheme for network processing.
Proceedings of the 21st Asia-Pacific Conference on Communications, 2015

2012
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction.
Proceedings of the Global Communications Conference, 2011

2005
Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks.
IEICE Trans. Commun., 2005

1998
Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998


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