Kazuhiko Kajigaya

According to our database, Kazuhiko Kajigaya authored at least 12 papers between 1990 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Long-Retention-Time, High-Speed DRAM Array with 12-<i>F</i>² Twin Cell for Sub 1-V Operation.

Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara

IEICE Trans. Electron., 2007

DRAM and eRAM.

Martin Brox, Kazuhiko Kajigaya

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM.

Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara

IEEE J. Solid State Circuits, 2006

2005

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router.

Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara

IEEE J. Solid State Circuits, 2005

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.

Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara

Proceedings of IEEE International Conference on Communications, 2005

2002

A low-impedance open-bitline array for multigigabit DRAM.

Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura

IEEE J. Solid State Circuits, 2002

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs.

Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya

IEEE J. Solid State Circuits, 2001

1997

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory.

Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya

IEEE J. Solid State Circuits, 1997

1996

A 29-ns 64-Mb DRAM with hierarchical array architecture.

Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

IEEE J. Solid State Circuits, 1996

1991

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto

IEEE J. Solid State Circuits, November, 1991

1990

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1990