Kazimierz Wiatr
Orcid: 0000-0001-5959-0277Affiliations:
- AGH University of Science and Technology, Poland
According to our database1,
Kazimierz Wiatr
authored at least 70 papers
between 1997 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Computer-Aided Cytology Diagnosis in Animals: CNN-Based Image Quality Assessment for Accurate Disease Classification.
CoRR, 2023
CoRR, 2023
Using super-resolution for enhancing visual perception and segmentation performance in veterinary cytology.
CoRR, 2023
Segmentation of the veterinary cytological images for fast neoplastic tumors diagnosis.
CoRR, 2023
2022
Canine age classification using Deep Learning as a step towards preventive medicine in animals.
Proceedings of the 17th Conference on Computer Science and Intelligence Systems, 2022
2021
Proceedings of the Intelligent Computing, 2021
2020
A study of the loops control for reconfigurable computing with OpenCL in the LABS local search problem.
Int. J. High Perform. Comput. Appl., 2020
Comput. Sci., 2020
The Choice of Feature Representation in Small-Scale MobileNet-Based Imbalanced Image Recognition.
Proceedings of the 15th International Joint Conference on Computer Vision, 2020
2019
How orthogonal are we? A note on fast and accurate inner product computation in the floating-point arithmetic.
Proceedings of the First International Conference on Societal Automation, 2019
2018
Design of a Visual Front-End for Parallel Signal Processing on Underwater Search Drone.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018
2017
Comput. Informatics, 2017
Comput. Informatics, 2017
Proceedings of the Parallel Processing and Applied Mathematics, 2017
ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
Formal Analysis of HTM Spatial Pooler Performance Under Predefined Operation Conditions.
Proceedings of the Rough Sets - International Joint Conference, 2016
Proceedings of the 8th International Conference on Agents and Artificial Intelligence (ICAART 2016), 2016
Study of the Parallel Techniques for Dimensionality Reduction and Its Impact on Performance of the Text Processing Algorithms.
Proceedings of the 8th International Conference on Agents and Artificial Intelligence (ICAART 2016), 2016
Using Spatial Pooler of Hierarchical Temporal Memory for object classification in noisy video streams.
Proceedings of the 2016 Federated Conference on Computer Science and Information Systems, 2016
2015
Proceedings of the Parallel Processing and Applied Mathematics, 2015
Energy Efficient Calculations of Text Similarity Measure on FPGA-Accelerated Computing Platforms.
Proceedings of the Parallel Processing and Applied Mathematics, 2015
2014
Proceedings of the Intelligent Tools for Building a Scientific Information Platform: From Research to Implementation, 2014
Comput. Informatics, 2014
Proceedings of the eScience on Distributed Computing Infrastructure, 2014
2013
The Enhancement of a Computer System for Sorting Capabilities Using FPGA Custom Architecture.
Comput. Informatics, 2013
Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C.
Comput. Informatics, 2013
Comparison of Hybrid Sorting Algorithms Implemented on Different Parallel Hardware Platforms.
Comput. Sci., 2013
Comput. Sci., 2013
The Regular Expression Matching Algorithm for the Energy Efficient Reconfigurable SoC.
Proceedings of the Parallel Processing and Applied Mathematics, 2013
Development of Domain-Specific Solutions Within the Polish Infrastructure for Advanced Scientific Research.
Proceedings of the Parallel Processing and Applied Mathematics, 2013
Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
2012
Proceedings of the Intelligent Tools for Building a Scientific Information Platform, 2012
Proceedings of the Building a National Distributed e-Infrastructure - PL-Grid, 2012
2011
The implementation of the customized, parallel architecture for a fast word-match program.
Comput. Syst. Sci. Eng., 2011
Grand Challenges Less Challenging: New Possibilities Provided by Graphics Processing Units.
Bio Algorithms Med Syst., 2011
Proceedings of the Parallel Processing and Applied Mathematics, 2011
Image Contents Annotations with the Ensemble of One-class Support Vector Machines.
Proceedings of the NCTA 2011, 2011
2010
Analysis of the Basic Implementation Aspects of Hardware-Accelerated Density Functional Theory Calculations.
Comput. Informatics, 2010
Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration.
Int. J. Appl. Math. Comput. Sci., 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform.
Comput. Informatics, 2009
E-learning and blackboard platform at ACC CYFRONET AGH.
Bio Algorithms Med Syst., 2009
Using Standard Hardware Accelerators to Decrease Computation times in Scientific Applications.
Comput. Sci., 2009
Hardware Implementation of the Exponent Based Computational Core for an Exchange-Correlation Potential Matrix Generation.
Proceedings of the Parallel Processing and Applied Mathematics, 2009
Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function.
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Comput. Sci., 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Proceedings of the FPL 2007, 2007
Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2004
Chen and Loeffler Fast DCT modified Algorithms Implemented in FPGA Chips for Real-Time Image Compression.
Proceedings of the International Conference on Computer Vision and Graphics, 2004
2002
Median and Morphological Specialized Processors for a Real-Time Image Data Processing.
EURASIP J. Adv. Signal Process., 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 27th EUROMICRO Conference 2001: A Net Odyssey, 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
2000
Embedded Zero Wavelet Coefficient Coding Method for FPGA Implementation of Video Codec in Real-Time Systems.
Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000
Implementation Image Data Convolutions Operations in FPGA Reconfigurable Structures for Real-Time Vision Systems.
Proceedings of the 2000 International Symposium on Information Technology (ITCC 2000), 2000
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
1999
MISD Architecture of Specialized Processors in FPGA Structures for a Real-Time Video Data Pre-Processing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
1998
Pipeline Architecture of Specialized Reconfigurable Processors in FPGA Structures for Real-Time Image Pre-Processing.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
1997
Dedicated Hardware Processors for a Real-Time Image Data Pre-processing Implemented in FPGA Structure.
Proceedings of the Image Analysis and Processing, 9th International Conference, 1997
Specialised architecture of dedicated hardware processors for real-time image data pre-processing.
Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, 1997