Kayode Sanni

Orcid: 0000-0002-7694-3983

Affiliations:
  • Johns Hopkins University, Department of Electrical and Computer Engineering, Baltimore, MD, USA


According to our database1, Kayode Sanni authored at least 8 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2023
A RISC-V Neuromorphic Micro-Controller Unit (vMCU) with Event-Based Physical Interface and Computational Memory for Low-Latency Machine Perception and Intelligence at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2019
A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Mixed-Signal Successive Approximation Architecture for Energy-Efficient Fixed-Point Arithmetic in 16nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Bio-Inspired Human Action Recognition With a Micro-Doppler Sonar System.
IEEE Access, 2018

A Charge-Based Architecture for Energy-Efficient Vector-Vector Multiplication in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
Bio-inspired system architecture for energy efficient, BIGDATA computing with application to wide area motion imagery.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
FPGA emulation of a spike-based, stochastic system for real-time image dewarping.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

FPGA implementation of a Deep Belief Network architecture for character recognition using stochastic computation.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015


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