Kavitha T. Madhu

According to our database, Kavitha T. Madhu authored at least 10 papers between 2014 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Autotuning LSTM for Accelerated Execution on Edge.

Aditi Saluja, Arnab Mitra, Ankur Deshwal, Kavitha T. Madhu, Ujjawal Chugh, Seungwon Lee, Joonho Song

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Transport Triggered near Memory Accelerator for Deep Learning.

Kavitha T. Madhu, Saptarsi Das, Abhishek Tyagi, Ankur Deshwal, Joonho Song, Seungwon Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2017

Energy aware synthesis of application kernels through composition of data-paths on a CGRA.

Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan

Integr., 2017

REDEFINE^®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress).

Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton

Proceedings of the 2017 International Conference on Compilers, 2017

2016

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.

Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Flexible resource allocation and management for application graphs on ReNÉ MPSoC.

Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Krishna C. Madhava, S. K. Nandy, Ranjani Narayan

Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016

2015

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.

Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Compiling HPC Kernels for the REDEFINE CGRA.

Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.

Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan

J. Syst. Archit., 2014

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.

Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014