Kavita Khare

Orcid: 0000-0002-7704-7646

According to our database1, Kavita Khare authored at least 28 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs.
IEEE Embed. Syst. Lett., June, 2024

2023
ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error.
Int. J. Circuit Theory Appl., 2022

2021
A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique.
IEEE Access, 2021

2019
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology.
Circuits Syst. Signal Process., 2019

2018
New Leakage Reduction Techniques for FinFET Technology with Its Application.
J. Circuits Syst. Comput., 2018

2016
Concept, Design, and Implementation of Reconfigurable CORDIC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Power High Speed 1-bit Full Adder Circuit Design.
ICTCS, 2016

Leakage Power Reduction Technique by using FinFET Technology.
ICTCS, 2016

2013
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence.
J. Signal Process. Syst., 2013

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

CORDIC-based window implementation to minimise area and pipeline depth.
IET Signal Process., 2013

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits.
Circuits Syst. Signal Process., 2013

Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012
FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems.
J. Signal Process. Syst., 2012

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency.
Int. J. Reconfigurable Comput., 2012

Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm.
Comput. J., 2012

Hardware Efficient Architecture for Generating Sine/Cosine Waves.
Proceedings of the 25th International Conference on VLSI Design, 2012

2011
VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks.
Eur. Trans. Telecommun., 2011

2010
Standby leakage reduction in nanoscale CMOS VLSI circuits.
Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

2009
Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks.
Proceedings of the ARTCom 2009, 2009

FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers.
Proceedings of the ARTCom 2009, 2009

2008
100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation.
Proceedings of the 16th International Conference on Networks, 2008


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