Kaviraj Chopra

According to our database, Kaviraj Chopra authored at least 22 papers between 2004 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis.

Cheng Zhuo, Kaviraj Chopra, Dennis Sylvester, David T. Blaauw

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques.

Vineeth Veetil, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Victim Alignment in Crosstalk-Aware Timing Analysis.

Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

Statistical Performance Analysis Optimization of Digital Circuits.

Kaviraj Chopra

PhD thesis, 2008

A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.

Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Statistical Timing Analysis: From Basic Principles to State of the Art.

David T. Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A statistical approach for full-chip gate-oxide reliability analysis.

Kaviraj Chopra, Cheng Zhuo, David T. Blaauw, Dennis Sylvester

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Transistor-Specific Delay Modeling for SSTA.

Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.

Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Victim alignment in crosstalk aware timing analysis.

Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Top-k Aggressors Sets in Delay Noise Analysis.

Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer

Proceedings of the 44th Design Automation Conference, 2007

2006

Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States.

Kaviraj Chopra, Sarma B. K. Vrudhula

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis and modeling of CD variation for statistical static timing.

Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A new statistical max operation for propagating skewness in statistical timing analysis.

Kaviraj Chopra, Bo Zhai, David T. Blaauw, Dennis Sylvester

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An efficient static algorithm for computing the soft error rates of combinational circuits.

Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.

Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David T. Blaauw, Dennis Sylvester

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Statistical Timing Based Optimization using Gate Sizing.

Aseem Agarwal, Kaviraj Chopra, David T. Blaauw

Proceedings of the 2005 Design, 2005

CAD tools for variation tolerance.

David T. Blaauw, Kaviraj Chopra

Proceedings of the 42nd Design Automation Conference, 2005

Circuit optimization using statistical static timing analysis.

Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov

Proceedings of the 42nd Design Automation Conference, 2005

2004

Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.

Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Framework for Battery-Aware Sensor Management.

Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan

Proceedings of the 2004 Design, 2004

Implicit pseudo boolean enumeration algorithms for input vector control.

Kaviraj Chopra, Sarma B. K. Vrudhula

Proceedings of the 41th Design Automation Conference, 2004